In a liquid crystal display comprising a plurality of gate lines and data lines, and an array of pixels arranged between adjacent gates lines and data lines, it is desirable to maintain the voltage potential on a pixel (m, n) over a reasonable period of time after the signal at the gate-line has changed from an H-state (Vgh) to an L-state (Vgl). The voltage potential is maintained by the charge capacity of each pixel. The charge is partially stored in the liquid crystal layer between the pixel electrodes, one of which is connected to a common electrode and the other is connected to the data line n through a switching element. As shown in FIG. 1, the charge capacity associated with the liquid crystal layer is represented by Clc, and the switching element is a TFT. In order to increase the charge storage capacity, a charge storage capacitor Cst is connected in parallel to the electrodes and another capacitor Cgs is connected in parallel to the TFT.
As the signal at the gate-line m changes from Vgh to Vgl, the drop in the voltage potential across the storage capacitor Cgs causes the voltage potential in the pixel relative to the common electrode to reduce by an amount ofΔVf=Cgs(Vgh−Vgl)/(Cgs+Clc+Cst).  (1)The drop in the voltage potential in the pixel, as illustrated in FIG. 2, is known as the feed-through potential drop. The feed-through potential drop significantly affects the contrast in a black-and-white (B/W) LCD device and the shape of the gamma curve in a color LCD device.
In prior art, a different shape of the gate line signal is used to compensate for the drop in the voltage potential. As shown in FIG. 3, one end of the storage capacitor Cst is connected to an adjacent gate-line m−1, instead of the common line. Furthermore, the signal on the gate lines has three voltage levels Vgh, Vgc and Vgl, as shown in FIG. 4, instead of two levels Vgh and Vgl. When the signal on the gate line m+1 is changed from Vgl to Vgh, the signal on the gate line m−1 is changed from Vgc to Vgl. As a result, the voltage potential in pixel (m, n) is pulled upward in a first step. When the signal on the gate-line m is changed from Vgc to Vgl, the voltage potential at pixel (m, n) is further pulled upward in a second step. As such, the feed-through potential drop can be partially compensated. In such a scheme, Vgc is determined by Vgh, Vgl, Cst and Cgs as follows:(Vgc−Vgl)Cst=(Vgl−Vgh)Cgs  (2)
This three-step gate-line signal is useful only when the storage capacitors Cst are tied to the gate lines, but it cannot be used when the storage capacitors Cst are tied to the common lines.